1. Field of the Invention
The present invention relates to a high-frequency device in which a high-frequency circuit is integrated on a semi-conductor chip, more particularly to a high-frequency device whose size is decreased by using a chip sized package and high-frequency characteristic is improved.
2. Description of the Related Art
Wide spread of portable communication apparatuses created a demand for low-cost, compact and highly functional devices which are to be mounted thereupon. There are high-frequency devices that use a silicon substrate in order to reduce cost. It was suggested to form high-frequency circuits on a silicon substrate rather than on more expensive gallium-arsenic substrate of the conventional type. Furthermore, a chip sized package or chip scale package (CSP) is used to decrease the size. A chip sized package has a structure in which a sealing electrically insulating layer composed of a resin such as a polyimide is formed by a mold molding method on a semiconductor chip substrate, thereby sealing the semiconductor chip. In such a structure, the package size is the same as the chip size and high-density mounting is possible. A highly functional device is obtained by forming a receiving circuit and a transmitting circuit in the same semiconductor chip, and transmission and reception of high-frequency signals, modulation and demodulation of the signals, and processing of base band signals can be conducted in a single chip. Therefore, various high-frequency signals pass through input and output terminals of a single chip and high-frequency characteristics at the input and output terminals have to be taken into account.
A flip chip bonding (FCB) method has been suggested as a method for miniaturizing semiconductor devices. The flip chip bonding method represents a technology by which a plurality of solder balls are provided as input and output terminals on the surface of a semiconductor chip and the semiconductor chip is bonded to a package substrate via those solder balls, thereby making it possible to connect a large number of input and output terminals of the chip to the terminals of the package substrate, without using wire bonding, and to decrease the package size accordingly.
A variety of methods have been suggested for increasing the high-frequency characteristics of input and output terminals in semiconductor devices using such a flip chip bonding method. Examples of those methods are described in Japanese Patent Applications Laid-open No. H09-306917, H10-64953, and 2002-313930. Japanese Patent Application Laid-open No. H09-306917 described a structure in which, among the pads where solder bumps are formed, the surface area of high-frequency input and output pads which are used for inputting and outputting high-frequency signals is made small, whereas the surface area of other pads which are not used for inputting and outputting high-frequency signals is made large. In this structure, decreasing the surface area of high-frequency input and output pads which are used for inputting and outputting high-frequency signals makes it possible to decrease the parasitic impedance to the semiconductor substrate and to reduce the signal loss.
Japanese Patent Application Laid-open No. H10-64953 describes that when electrically conductive connection terminals called electrically conductive pillars are formed on a GaAs semiconductor substrate, the correlation between the opening diameter and the height of the connection terminals in a plating process is employed, short connection terminals are formed by reducing the opening diameter, long connection terminal are formed by increasing the opening diameter, and the heights of the connection terminals of the two types are adjusted. As a result, short connection terminals with a low resistance can be formed, and the impedance and capacitance of the connection terminals of a high-frequency semiconductor chip can be reduced.
Japanese Patent Application Laid-open No. 2002-313930 describes a semiconductor device obtained by flip chip bonding using a ball grid array, wherein shielding wiring layers connected to a reference potential are formed above and below a metal wiring, and a strip line structure is formed to obtain a constant characteristic impedance of the metal wiring where a high-frequency signal propagates.
The above-described Japanese Patent Applications Laid-open No. H9-306917, H10-64953, and 2002-313930 relate to flip chip bonding by which chips are bonded inside a package and the package size is larger than the chip size. Therefore, from the standpoint of miniaturization, the configurations of the above publications are different from that of the chip sized package.
An example of a chip sized package is described in Japanese Patent Application Laid-open No. 2003-243570. In this example, a sealing resin layer composed of a polyamide is formed on a semiconductor substrate, posts for input and output terminals are formed inside the sealing resin layer, and an impedance matching circuit of input/output terminals is formed by forming an inductor element on the interface of the semiconductor substrate and the sealing resin layer. Because the package state is obtained by forming a sealing resin layer on the surface of a semiconductor chip, the size can be reduced comparing to that of the package of a flip chip type, and a compact semiconductor device that can be installed in portable communication devices can be effectively obtained.
Thus, chip sized packages have an advantage over the flip chip packages in terms of miniaturization. However, the sealing electrically insulating layer or resin layer having a sealing function are much thicker than the multilayer wiring layers on the chip surface, the height of the electrically conductive posts formed in the resin layer becomes rather large, and the characteristics relating to high-frequency signals are seriously degraded. Of the high-frequency signals, with respect to low-power high-frequency signals, a configuration is required which allows the degradation of the loss characteristic thereof to be avoided, and with respect to high-power high-frequency signals, a configuration is required which has a sufficient current supply capability in addition to the loss characteristic. Furthermore, coupling of a high-frequency circuit on the mounting substrate with a high-frequency circuit on the semiconductor chip should be suppressed for a higher frequency band.